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APW7074
Synchronous Buck PWM Controller
Features
* * * * * * * * * *
Single 12V Power Supply Required 0.8V Reference with 1% Accuracy Shutdown and Soft-start Function 300KHz Fixed Switching Frequency Voltage Mode PWM Control Design Up to 100% Duty Cycle Under-Voltage Protection Over-Current Protection SOP-14 Package Lead Free Available (RoHS Compliant)
General Description
The APW7074 uses fixed 300KHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates all of the control, monitoring and protecting functions into a single package, provides one controlled power output with under-voltage and over-current protections. The APW7074 provides excellent regulation for output load variation. The internal 0.8V temperaturecompensated reference voltage is designed to meet the requirement of low output voltage applications. The APW7074 with excellent protection functions: POR, OCP and UVP. The Power-On-Reset (POR) circuit can monitor the VCC, EN, and OCSET voltage to make sure the supply voltage exceeds their threshold voltage while the controller is running. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the upper and lower MOSFET' RDS(ON). When the output curs rent reaches the trip point, the controller will run the soft-start function until the fault events are removed. The Under-Voltage Protection (UVP) monitors the voltage at FB pin (VFB) for short-circuit protection, when the VFB is less 50% VREF, the controller will shutdown the IC directly.
Applications
*
Graphic Cards
Pin Outs
NC OCSET SS COMP FB EN GND 1 2 3 4 5 6 7 SOP-14 TOP V IEW 14 13 12 11 10 9 8 V CC PV CC LGA TE PGND BOOT UGA TE PHASE
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006 1 www.anpec.com.tw
APW7074
Ordering and Marking Information
APW7074 Lead Free Code Handling Code Temp. Range Package Code APW7074 K : APW7074 XXXXX Package Code K : SOP - 14 Temp. Range E : -20 to 70C Handling Code TU : Tube Lead Free Code L : Lead Free Device
TR : Tape & Reel Blank : Original Device
XXXXX- Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC OCSET GND
BOOT EN Power-On Reset IOCSET 200uA UGATE O.C.P Comparator VCC 0.27V Soft Start O.C.P Comparator 50%VREF :2 U.V.P Comparator PVCC PWM Comparator Error Amp VREF Oscillator Sawtooth Wave FOSC 300KHz PGND PHASE
ISS 10uA SS
Gate Control
LGATE
FB
COMP
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APW7074
Absolute Maximum Ratings
Symbol VCC, PVCC BOOT UGATE LGATE PHASE OCSET FB, COMP PGND TJ TSTG TSDR VESD VCC, PVCC to GND BOOT to PHASE UGATE to PHASE <400ns pulse width >400ns pulse width LGATE to PGND PHASE to GND OCSET to GND FB, COMP to GND PGND to GND Junction Temperature Range Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating <400ns pulse width >400ns pulse width <400ns pulse width >400ns pulse width Parameter Rating -0.3 to +16 -0.3 to +16 -5 to BOOT+5 -0.3 to BOOT +0.3 -5 to PVCC+5 -0.3 to BOOT +0.3 -5 to +21 -0.3 to 16 VCC+0.3 -0.3 to 7 -0.3 to +0.3 -20 to +150 -65 ~ 150 300 2 Unit V V V V V V V V C C C KV
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VCC, PVCC VIN VOUT IOUT TA TJ IC Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 to 13.2 2.2 to 13.2 0.8 to 5 0 to 25 -20 to 70 -20 to 125 Unit V V V A C C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70C. Typical values are at TA=25C.
Symbol
Parameter
Test Conditions
APW7074 Min Typ Max
Unit
INPUT SUPPLY CURRENT ICC VCC Supply Current (Shutdown mode) VCC Supply Current
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006
UGATE, LGATE and EN = GND UGATE and LGATE Open
3
0.5 5
1 10
mA mA
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APW7074
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70C. Typical values are at TA=25C.
Symbol
Parameter
Test Conditions
APW7074 Min 9 7.5 Typ 9.5 8 1.3 0.1 1.3 0.1 Max 10.0 8.5
Unit
POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold VOCSET Hysteresis Voltage Rising EN threshold Voltage EN Hysteresis Voltage OSCILLATOR FOSC VOSC Duty VREF Oscillator Frequency Ramp Amplitude Duty Cycle Range Reference Voltage Reference Voltage Tolerance PWM ERROR AMPLIFIER Gain SR Open Loop Gain Slew Rate FB Input Current VCOPM COMP High Voltage VCOPM COMP Low Voltage ICOMP COMP Source Current ICOMP COMP Sink Current GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE Lower Gate Source Current ILGATE Lower Gate Sink Current RUGATE Upper Gate Sink Impedance BOOT = 12V, VUGATE -VPHASE = 2V BOOT = 12V, VUGATE -VPHASE = 2V PVCC = 12V, VLGATE = 2V PVCC = 12V, VLGATE = 2V BOOT = 12V, IUGATE = 0.1A 2.6 1.05 4.9 1.4 2 1.6 3 2.4 A A A A VCOMP = 2V VCOMP = 2V RL = 10k, CL = 10pF (Note3) RL = 10k, CL = 10pF (Note3) RL = 10k, CL = 10pF (Note3) VFB = 0.8V 88 15 6 0.1 5.5 0 5 5 1 dB MHz V/us uA V V mA mA GBWP Open Loop Bandwidth -1 (nominal 1.35V to 2.95V) 0 0.80 +1 255 300 1.6 100 345 kHz V % V % V V V V V V
REFERENCE
RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A
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APW7074
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70C. Typical values are at TA=25C.
Symbol
Parameter
Test Conditions
APW7074 Min Typ 1.3 1.25 20 Max 1.95 1.88
Unit
GATE DRIVERS (Cont.) RLGATE RLGATE TD UVFB IOCSET VOCP ISS Lower Gate Source Impedance Lower Gate Sink Impedance Dead Time FB Under Voltage Level OCP Voltage (Low-Side) Soft-Start Charge Current Percent of VREF 45 150 230 8 PVCC = 12V, ILGATE = 0.1A PVCC = 12V, ILGATE = 0.1A nS 55 250 310 12 % uA mV uA
PROTECTION 50 200 270 10
OCSET Source Current (Hi-Side) VOCSET = 11.5V
SOFT START
Note 3:Guaranteed by design.
Typical Application Circuit
1uF
12V PVCC VCC OCSET EN OFF SS
22nF
1N4148 1nF 1uF 2.37K 1uH
VIN
ON
470uFx2
470uF
BOOT
0.1uF
UGATE PHASE
APM2509 2.2uH
VOUT
1.5nF APM2506 SCD24 7.5R 1000uFx2
COMP FB GND
2.7K 1K
LGATE PGND
33nF 8.2nF
2K
18R
68nF
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APW7074
Function Pin Descriptions
VCC (Pin14) Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage by this pin. It is recommended that a decoupling capacitor (1 to 10uF) be connected to GND for noise decoupling. PVCC (Pin13) This pin provides a supply voltage for the lower gate drive, connect this pin to VCC pin in normal use. BOOT (Pin10) This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. PHASE (Pin8) This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection. GND (Pin7) This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND (Pin11) This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. COMP (Pin4) This pin is the output of PWM error amplifier. It is used to set the compensation components. FB (Pin5) This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection; if the FB voltage is under 50% of reference voltage, the device will be shut down. EN (Pin6) Pull this pin above 1.3V to enable the device and pull this pin below 1.2V to disable the device. In shutdown, the SS is discharged and the UGATE and LGATE pins are held low. Note that don' leave this pin open. t UGATE (Pin9) This pin is the gate driver for the upper MOSFET of PWM output. LGATE (Pin12) This pin is the gate driver for the lower MOSFET of PWM output. SS (Pin3) Connect a capacitor to GND and a 10uA current source charges this capacitor to set the soft-start time. OCSET (Pin2) This pin serves two functions: a shutdown control and the setting of over current limit threshold. Pulling this pin below 1.3V will shutdown the controller, forcing the UGATE and LGATE signals to be low. A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over current limit. An internal 200uA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the high side MOSFET. The threshold of the over current limit is therefore given by:
IPEAK = IOCSET (200uA ) x R OCSET R DS(ON)
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APW7074
Typical Characteristics
Power On
CH1
Power Off
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH2 CH1
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH2
CH3
CH3
CH1: Vcc (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 10ms/div
CH1: Vcc (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 2ms/div
EN (EN=Vcc)
CH1
Shutdown (EN=GND)
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH1
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH2
CH2
CH3
CH3
CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div
CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div
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APW7074
Typical Characteristics
UGATE Rising
UGATE Falling
CH1
CH1 CH2
VCC=12V, Vin=12V Vo=1.5V, L=1uH
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH2
CH3
CH3
CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div
CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ms/div
Load Transient Response
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH1
Under Voltage Protection
CH1
VCC=12V, Vin=12V Vo=1.5V, L=1uH
CH2
CH3
CH4
CH2
CH1: Vo (500mV/div) CH2:Io (5A/div) Time: 200us/div
CH1: SS (5V/div) CH2: Io (5A/div) CH3: Vo (1V/div) CH4: Ug (10V/div) Time: 50ms/div
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APW7074
Typical Characteristics
Over Current Protection
CH1
Short Test
Vcc=12V, Vin=12V Vo=1.5V, L=1uH
CH1
Vcc=12V, Vin=12V,Vo=1.5V, L=1uH Rocset=1K[ , Rds(on)=8m[
CH2
CH3
CH2
CH3
CH4 CH4
CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4:Ug (20V/div) Time: 10ms/div
CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4:Ug (20V/div) Time: 10ms/div
Switching Frequency vs. Junction Temperature
310 305 300 295 290 285 280 275 -40
Reference Voltage vs. Junction Temperature
0.804
Switching Frequency(KHz)
0.802
Reference Voltage(V)
-20 0 20 40 60 80 100 120
0.8
0.798 0.796
0.794
0.792 -40
-20
0
20
40
60
80
100
120
Junction Temperature (C)
Junction Temperature (C)
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APW7074
Typical Characteristics
UGATE Source current vs. UGATE Voltage
3.5
UGATE Sink current vs. UGATE Voltage
3
VBOOT=12V
3
VBOOT=12V
2.5
UGATE Source Current (A)
2.5 2 1.5 1 0.5 0 0 2 4 6 8 10 12
UGATE Sink Current (A)
2 1.5 1 0.5 0 0 2 4 6 8 10 12
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source current vs. LGATE Voltage
6
LGATE Sink current vs. LGATE Voltage
3.5
LGATE Source Current (A)
5 4
PVCC=12V
LGATE Sink Current (A)
3 2.5 2 1.5 1 0.5 0
PVCC=12V
3 2
1 0 0 2 4 6 8 10 12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
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APW7074
Function Descriptions
Power On Reset (POR) The Power-On Reset (POR) function of APW7074 continually monitors the input supply voltage (VCC), the enable (EN) pin and OCSET pin. The supply voltage (VCC) must exceed its rising POR threshold voltage. The voltage at OCSET pin is equal to VIN less a fixed voltage drop (Vocset = VIN- VROCSET). EN pin can be pulled high with connecting a resistor to VCC. The POR function initiates soft-start operation after VCC, EN and OCSET voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (EN pin low). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Soft-Start/EN The SS/EN pins control the soft-start and enable or disable the controller. Connect a soft-start capacitor from SS pin to GND to set the soft-start interval. Figure1. shows the soft-start interval. When VCC reaches its Power-On-Reset threshold (9.5V), internal 10uA current source starts to charge the capacitor. When the SS reaches the enabled threshold about 1.8V, the internal 0.8V reference starts to rise and follows the SS; the error amplifier output (COMP) suddenly raises to 1. 35V, which is the valley of the triangle wave of the oscillator, leads the VOUT to start up. Until the SS reaches about 4.2V, the internal reference completes the soft-start interval and reaches to 0.8V; then VOUT is in regulation. The SS still rises to 5.5V and then stops. C TSoft - Start = t 2 - t 1 = SS 2.4 V ISS Where: CSS = external Soft-Start capacitor ISS = Soft-Start current=10uA A resistor (ROCSET) connected between OCSET pin and the drain of the upper MOSFET will determine the over current limit. An internal 200uA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the upper MOSFET. When the voltage across the upper MOSFET exceeds the voltage drop across the R OCSET, an over-current will be detected. The threshold of the over current limit is therefore given by: Over-Current Protection (monitor upper MOSFET) The APW7074 provides two manners to protect the converter from abnormal output load; one monitors the voltage across the upper MOSFET and use the OCSET pin to set the over-current trip point, the other monitors the voltage across the lower MOSFET by comparing with an internal reference voltage (0.27V).
t0 t1 t2 Time 1.8V VOUT 4.2V VSS Voltage
Figure 1. Soft-Start Internal
ILIMIT =
IOCSET x R OCSET R DS (ON )
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined.
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APW7074
Function Descriptions (Cont.)
Over-Current Protection (Cont.) - The MOSFET'RDS(ON) is varied by temperature and gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer' datasheet. s - The minimum IOCSET (170uA) and minimum ROCSET should be used in the above equation. - Note that the ILIMIT is the current flow through the upper MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. An over current condition will shut down the device and discharge the CSS with a 10uA sink current and then initiate the soft-start sequence. If the over current condition is not removed during the soft-start interval, the device will be shut down while the over current is detected and the SS still rises to 4V to complete its cycle. The soft start function will be cycled until the over current condition is removed. Both over-current protections have the same behavior while an over current condition is detected. Over-Current Protection (monitor lower MOSFET) The other over-current protection monitors the output current by using the voltage drop across the lower MOSFET' RDS(ON) and this voltage drop will be coms pared with the internal 0.27V reference voltage. If the voltage drop across the lower MOSFET' RDS(ON) is s larger than 0.27V, an over-current condition is detected. The threshold of the over current limit is given by:
ILIMIT =
0.27V R DS(ON)
For the over-current is never occurred in the normal operating load range; the parameters RDS(ON) and ILIMIT in the above equation also have the same notices as the previous section. Under Voltage Protection The FB pin is monitored during converter operation by their own Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter' output is latched to be s floating.
Application Information
Output Voltage Selection The output voltage can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor' ripple current and s induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by:
R VOUT = 0.8 x 1 + OUT R GND

IRIPPLE =
VIN - VOUT VOUT x FS x L VIN
Where ROUT is the resistor connected from VOUT to FB and RGND is the resistor connected from FB to GND.
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VOUT = IRIPPLE x ESR
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APW7074
Application Information (Cont.)
Output Inductor Selection (Cont.) where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor' ripple current and the s regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) Where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW , is a function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the "RDS(ON) vs Temperature" curve of the power MOSFET.
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APW7074
Application Information (Cont.)
PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB and VOUT should be added. The compensation network is shown in Fig. 5. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by:
GAIN
LC
The PWM modulator is shown in Figure 4. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by:
GAIN PWM = VIN V OSC
VIN OSC GVOSC Driver PWM Comparator PHASE
1 + s x ESR x C OUT =2 s x L x C OUT + s x ESR x C OUT + 1
The poles and zero of this transfer functions are: 1 FLC = 2 x x L x C OUT
Output of Error Amplifier Driver
FESR =
1 2 x x ESR x C OUT
Figure 4. The PWM Modulator The compensation network is shown in Figure 5. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by:
COUT
The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor.
PHASE L OUTPUT
GAIN
ESR
AMP
V = COMP V OUT
1 1 // R2 + sC1 sC2 = 1 R1// R3 + sC3
Figure 2. The Output LC Filter
FLC -40dB/dec GAIN (dB)
1 1 s + x s + (R1 + R3 ) x C3 R2 x C2 R1 + R3 = x C1 + C2 1 R1 x R3 x C1 s s + x s + R2 x C1 x C2 R3 x C3
The poles and zeros of the transfer function are:
F Z1 = 1 2 x x R2 x C2
FESR -20dB/dec
F Z2 =
FP1 =
1 2 x x (R1 + R3 ) x C3
1 C1 x C2 2 x x R2 x C1 + C2
1 2 x x R3 x C3
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Frequency(Hz)
FP2 =
Figure 3. The LC Filter GAIN and Frequency
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APW7074
Application Information (Cont.)
PWM Compensation (Cont.)
C1 R3 VOUT R1 FB VREF VCOMP C3 R2 C2
5.Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations:
R1 FS -1 2 x FLC
Figure 5. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 6. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K.
GAIN (dB)
R3 =
C3 =
1 x R3 x FS
FZ1 FZ2
FP1
FP2
2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: VOSC FO R2 = x x R1 VIN FLC 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the equation: 1 C2 = 2 x x R2 x FLC x 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation:
20log (R2/R1)
20log (VIN/GVOSC)
Compensation Gain
FLC FESR PWM & Filter Gain Frequency(Hz) Converter Gain
Figure 6. Converter Gain and Frequency Layout Considerations In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic
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C1 =
C2 2 x x R2 x C2 x FESR - 1
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APW7074
Application Information (Cont.)
Layout Considerations (Cont.) circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. Figure 7. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed Figure 7.Layout Guidelines near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN and Phase nodes) should be a large plane for heat sinking.
APW7074 VCC PVCC BOOT UGATE PHASE LGATE
VIN
L O A D
VOUT
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006
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APW7074
Package Information
SOP - 14 (150mil)
E
H
0.015 x 45
D
C
A e B
GAUGE PLANE SEATING PLANE
A1
0.010
L
Dim A A1 B C D E e H L
Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0 6.215 1.274 8 0.228 0.015 0 Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150
Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006
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APW7074
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Tim e
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
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APW7074
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 350 <2.5 m m 240 +0/-5C 225 +0/-5C 2.5 m m 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0C* 260 +0C* 260 +0C* 1.6 m m - 2.5 m m 260 +0C* 250 +0C* 245 +0C* 2.5 m m 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006
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APW7074
Carrier Tape & Reel Dimensions(Cont.)
T2
J C A B
T1
Application
SOP-14 (150mil)
A 330REF F 7.5
B 100REF D 0.50 + 0.1
C 13.0 + 0.5 - 0.2 D1 1.50 (MIN)
J 2 0.5 Po 4.0
T1 16.5REF P1 2.0
T2 2.5 025 Ao 6.5
W 16.0 0.3 Ko 2.10
P 8 t 0.30.05
E 1.75
(mm)
Cover Tape Dimensions
Application SOP- 14 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Feb., 2006
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